tag:blogger.com,1999:blog-467992347672180293.post194352329584802066..comments2022-09-10T07:17:04.421-07:00Comments on Verification with Jigar: When Verification is complete ?Jigarhttp://www.blogger.com/profile/03384033267290360397noreply@blogger.comBlogger2125tag:blogger.com,1999:blog-467992347672180293.post-17219267407521934492010-12-21T05:47:50.529-08:002010-12-21T05:47:50.529-08:00No. You have to have TB/run test cases.
Formal i...No. You have to have TB/run test cases. <br /><br />Formal is equivalence check that says RTL sim behavior = Syntheses net list by using mathematical modelJigarhttps://www.blogger.com/profile/03384033267290360397noreply@blogger.comtag:blogger.com,1999:blog-467992347672180293.post-57489069911987417712010-11-30T10:01:14.229-08:002010-11-30T10:01:14.229-08:00Jigar,
Do you use formal verification to verify y...Jigar,<br /><br />Do you use formal verification to verify your design where you can explore the design functionality without creating a testbench or running simulations?<br /><br />AlokAlok Sanghavihttps://www.blogger.com/profile/13093933168919817609noreply@blogger.com