Verification with Jigar

When Verification is complete ?

2010-11-29T23:27:00.000-08:00

Obvious answer frontend verification engineer will give is when Functional Coverage matrix is 100% achieved as well as required code coverage is achieved (B,S,T,FSM - most frequently used).

To add to this one can answer When STA is done ensuring that timing constraint is met.Also since STA is done by mentioning some paths as ...*.... it is possible accidently we decalre some relevant path as false path , SO GLS is also prefred

Ans : Function Matrix/Code coverage matrix + STA + GLS (if not possible for all testcase at least for high priprity features)

Refer :
1> Code Coverage & Functional Coverage - ( http://verificationwithjigar.blogspot.com/2010/04/code-coverage-functional-coverage.html )

2> STA/Formal Verification Vs. Gatelevel ( http://verificationwithjigar.blogspot.com/2010/08/staformal-verification-vs-gatelevel.html )

Comments are welcomed.

SV Random thread stability

2010-11-24T04:59:00.000-08:00

For System Verilog users,

Has there been a situation in your project that at time X with tag X and seed =1 you got some XYZ input stimulus and after a while at time Y with tag Y if you use seed =1 the results changes ??

If yes than LRM section "Random Stability" is for you to read and understand,
Refer section 12.13

I will try to post example shortly.

Counter using D Flop only

2010-11-24T04:55:00.001-08:00

If I have a D-Flop only (USE OF ANY GATES NOT ALLOWED)and I am not worried about setup or hold violation (i.e. I can connnect output of flop to feed input without worrying violation) , How can you generate the 2 bit counter to count 00,01,10,11.

timescale directive question

2010-11-24T04:47:00.000-08:00

What Will be the output for

`timescale 2ns/100ps
module tb();
integer a;

initial
begin
#3.05 a =1'b1;
#100
a= 1'b0;
end
endmodule

What Will be time when intial block will end OR a = 1'b1 will execute.

No Simulation result please,your brain is enough.

Difference Between VMM and OVM

2010-09-22T23:48:00.000-07:00

What is the difference between VMM and OVM ?

1> One is program block is used in VMM but not in OVM. (This is one of the frequently asked technical question)

STA/Formal Verification Vs. Gatelevel

2010-08-26T03:42:00.000-07:00

Do We need GLS ? Can STA/Formal Verification Substitute it ?
Stayed tuned for my detailed comment,meanwhile you can post your response.

1> STA Covers all timing constraint on the other hand GLS does this for few paths(not all)

2> If by chance wrong desing undertanding leads to incorrect flase path/multicycle path than it can be avoided if GLS was done.

3> GLS provides power/switching information which STA will not provide. And yes everyone wants to know power usage.

4> GLS Provides Good check on Reset release,initialization.

Intelligent Testbench Automation

2010-08-25T01:59:00.000-07:00

Recently I attended EDA Tech Forum Seminar and learned something interesting which I am sharing.

Lets say functional plan is having bins for A from 255:0 and b from [7:0] you need to cover all values,So lets say we have to run test case 6000 times (> 2048 (256*8 = 2048)) to hit this.

Now problem in traditional SV constraint random environment is we don't have control over what no we generate, it is purely random and does not depend on previously generated no.

With Intelligent Test bench Automation We take history of already generated no in to account and based on that new no is generated so reaching 100 % is faster.

One may argue we can use randc and define the weightage but even after using this we see many times that same bin is hit no of times while the other bin is not hit because random no is not generated.

Lets say Your chip has input A and it affect output o1,o2 and there are no of paths to reach to 01,02 from A. Now to cover this using traditional approach will take long time compared to Intelligent Test bench.

Conclusion :

Intelligent Test bench Automation uses existing constraint randomization of SV but considers history of already generated number,allowing us to achieve functional coverage much faster. For this you need to add method infact.randomzie() ( I may be wrong here syntax wise. But it is not a lot of change in environment) and need to replace your stim. gen with mentor's tim gen.

Vector combination required

2010-08-23T03:31:00.000-07:00

If a design can be of AND,OR,XOR
How many different vector combination(stimulus) of input A and B is required to identify gate type?

GLS simulation X propogation by MUX

2010-08-17T03:29:00.000-07:00

I faced this issues while debugging GLS simulation.
Mux is having input A,B,S(sel), Z(output)

B=0 (always)
A= 0(20ns),1(20ns),0(20ns)
S = X throughout simulation

What should be output here? (This sounds very simple right, Think you may be correct or may not be)

I will post answer for this soon.

Code Coverage & Functional Coverage

2010-04-13T02:43:00.000-07:00

Code Coverage & Functional Coverage matrix can help to answer the question when verification is complete.(Verification completeness will depend on other parameters like bug rates,reviews, and other considerations as well.)

For example design having A,B,sel as input and Out as Output having functionality of +,-,/,* depending on sel line.

Assume the verification is only using code coverage which is indicating that line out = A*B is not covered in the code coverage.Now lets say one applies stimulus so that sel is for * operation.So now this is covered and my code coverage is 100 % Branch,Line,Toggle,Expression. Can I say verification is complete ?

No not yet. When coverage is 100 % it means whatever code has been written by designer is covered 100%. What if designer has missed to code functionality for example designer , lets say missed to implement division. In this case if verification engineer is only relying on coverage matrix he will not be able to capture the bug that designer has not implemented division functionality.

In concept Functional coverage ensures that all functionality has been implemented OR not. Code coverage also helps to identify missed scenario and hence possible bugs for example fifo_full signal is only covered 50 % (0 to 1 transition ) means that either there is no stimulus to that generates 1 to 0 transition OR fifo_full logic is written incorrectly in design such that it never generates transition from 1 to 0.

SV Question- Difference Between Mailbox and Semaphore

2010-04-13T01:35:00.000-07:00

Difference between mailbox and semaphore is very standard question asked in System Verilog interview,Some times it is asked indirectly.

Mailobox,Semaphore can pass the object or information(variable).For example, there are multiple driver looking to drive same interface(lets call interface A). If Verifciation environemtn uses Mailbox and provides packet to multiple driver,all of them is allowed access to packet and henace all can drive the interface A. This will create multiple driver on same interface.

In order to avoid this semaphore can be used which ensures that once driver X has access to object only driver X will be able to drive interface A. driver Y will have to wait till driver X returns the key so this will avoid multiple driver driving same interface.