STA/Formal Verification Vs. Gatelevel

Do We need GLS ? Can STA/Formal Verification Substitute it ?
Stayed tuned for my detailed comment,meanwhile you can post your response.


1> STA Covers all timing constraint on the other hand GLS does this for few paths(not all)

2> If by chance wrong desing undertanding leads to incorrect flase path/multicycle path than it can be avoided if GLS was done.

3> GLS provides power/switching information which STA will not provide. And yes everyone wants to know power usage.

4> GLS Provides Good check on Reset release,initialization.

Intelligent Testbench Automation

Recently I attended EDA Tech Forum Seminar and learned something interesting which I am sharing.

Lets say functional plan is having bins for A from 255:0 and b from [7:0] you need to cover all values,So lets say we have to run test case 6000 times (> 2048 (256*8 = 2048)) to hit this.

Now problem in traditional SV constraint random environment is we don't have control over what no we generate, it is purely random and does not depend on previously generated no.

With Intelligent Test bench Automation We take history of already generated no in to account and based on that new no is generated so reaching 100 % is faster.

One may argue we can use randc and define the weightage but even after using this we see many times that same bin is hit no of times while the other bin is not hit because random no is not generated.

Lets say Your chip has input A and it affect output o1,o2 and there are no of paths to reach to 01,02 from A. Now to cover this using traditional approach will take long time compared to Intelligent Test bench.

Conclusion :

Intelligent Test bench Automation uses existing constraint randomization of SV but considers history of already generated number,allowing us to achieve functional coverage much faster. For this you need to add method infact.randomzie() ( I may be wrong here syntax wise. But it is not a lot of change in environment) and need to replace your stim. gen with mentor's tim gen.

Vector combination required

If a design can be of AND,OR,XOR
How many different vector combination(stimulus) of input A and B is required to identify gate type?

GLS simulation X propogation by MUX

I faced this issues while debugging GLS simulation.
Mux is having input A,B,S(sel), Z(output)

B=0 (always)
A= 0(20ns),1(20ns),0(20ns)
S = X throughout simulation

What should be output here? (This sounds very simple right, Think you may be correct or may not be)

I will post answer for this soon.