When Verification is complete ?

Obvious answer frontend verification engineer will give is when Functional Coverage matrix is 100% achieved as well as required code coverage is achieved (B,S,T,FSM - most frequently used).

To add to this one can answer When STA is done ensuring that timing constraint is met.Also since STA is done by mentioning some paths as ...*.... it is possible accidently we decalre some relevant path as false path , SO GLS is also prefred

Ans : Function Matrix/Code coverage matrix + STA + GLS (if not possible for all testcase at least for high priprity features)

Refer :
1> Code Coverage & Functional Coverage - ( http://verificationwithjigar.blogspot.com/2010/04/code-coverage-functional-coverage.html )

2> STA/Formal Verification Vs. Gatelevel ( http://verificationwithjigar.blogspot.com/2010/08/staformal-verification-vs-gatelevel.html )

Comments are welcomed.

SV Random thread stability

For System Verilog users,

Has there been a situation in your project that at time X with tag X and seed =1 you got some XYZ input stimulus and after a while at time Y with tag Y if you use seed =1 the results changes ??

If yes than LRM section "Random Stability" is for you to read and understand,
Refer section 12.13

I will try to post example shortly.

Counter using D Flop only

If I have a D-Flop only (USE OF ANY GATES NOT ALLOWED)and I am not worried about setup or hold violation (i.e. I can connnect output of flop to feed input without worrying violation) , How can you generate the 2 bit counter to count 00,01,10,11.

timescale directive question

What Will be the output for

`timescale 2ns/100ps
module tb();
integer a;

initial
begin
#3.05 a =1'b1;
#100
a= 1'b0;
end
endmodule

What Will be time when intial block will end OR a = 1'b1 will execute.

No Simulation result please,your brain is enough.

Difference Between VMM and OVM

What is the difference between VMM and OVM ?

1> One is program block is used in VMM but not in OVM. (This is one of the frequently asked technical question)

STA/Formal Verification Vs. Gatelevel

Do We need GLS ? Can STA/Formal Verification Substitute it ?
Stayed tuned for my detailed comment,meanwhile you can post your response.


1> STA Covers all timing constraint on the other hand GLS does this for few paths(not all)

2> If by chance wrong desing undertanding leads to incorrect flase path/multicycle path than it can be avoided if GLS was done.

3> GLS provides power/switching information which STA will not provide. And yes everyone wants to know power usage.

4> GLS Provides Good check on Reset release,initialization.

Intelligent Testbench Automation

Recently I attended EDA Tech Forum Seminar and learned something interesting which I am sharing.

Lets say functional plan is having bins for A from 255:0 and b from [7:0] you need to cover all values,So lets say we have to run test case 6000 times (> 2048 (256*8 = 2048)) to hit this.

Now problem in traditional SV constraint random environment is we don't have control over what no we generate, it is purely random and does not depend on previously generated no.

With Intelligent Test bench Automation We take history of already generated no in to account and based on that new no is generated so reaching 100 % is faster.

One may argue we can use randc and define the weightage but even after using this we see many times that same bin is hit no of times while the other bin is not hit because random no is not generated.

Lets say Your chip has input A and it affect output o1,o2 and there are no of paths to reach to 01,02 from A. Now to cover this using traditional approach will take long time compared to Intelligent Test bench.

Conclusion :

Intelligent Test bench Automation uses existing constraint randomization of SV but considers history of already generated number,allowing us to achieve functional coverage much faster. For this you need to add method infact.randomzie() ( I may be wrong here syntax wise. But it is not a lot of change in environment) and need to replace your stim. gen with mentor's tim gen.