When Verification is complete ?

Obvious answer frontend verification engineer will give is when Functional Coverage matrix is 100% achieved as well as required code coverage is achieved (B,S,T,FSM - most frequently used).

To add to this one can answer When STA is done ensuring that timing constraint is met.Also since STA is done by mentioning some paths as ...*.... it is possible accidently we decalre some relevant path as false path , SO GLS is also prefred

Ans : Function Matrix/Code coverage matrix + STA + GLS (if not possible for all testcase at least for high priprity features)

Refer :
1> Code Coverage & Functional Coverage - ( http://verificationwithjigar.blogspot.com/2010/04/code-coverage-functional-coverage.html )

2> STA/Formal Verification Vs. Gatelevel ( http://verificationwithjigar.blogspot.com/2010/08/staformal-verification-vs-gatelevel.html )

Comments are welcomed.

SV Random thread stability

For System Verilog users,

Has there been a situation in your project that at time X with tag X and seed =1 you got some XYZ input stimulus and after a while at time Y with tag Y if you use seed =1 the results changes ??

If yes than LRM section "Random Stability" is for you to read and understand,
Refer section 12.13

I will try to post example shortly.

Counter using D Flop only

If I have a D-Flop only (USE OF ANY GATES NOT ALLOWED)and I am not worried about setup or hold violation (i.e. I can connnect output of flop to feed input without worrying violation) , How can you generate the 2 bit counter to count 00,01,10,11.

timescale directive question

What Will be the output for

`timescale 2ns/100ps
module tb();
integer a;

initial
begin
#3.05 a =1'b1;
#100
a= 1'b0;
end
endmodule

What Will be time when intial block will end OR a = 1'b1 will execute.

No Simulation result please,your brain is enough.