Hit Count

Wednesday, November 24, 2010

SV Random thread stability

For System Verilog users,

Has there been a situation in your project that at time X with tag X and seed =1 you got some XYZ input stimulus and after a while at time Y with tag Y if you use seed =1 the results changes ??

If yes than LRM section "Random Stability" is for you to read and understand,
Refer section 12.13

I will try to post example shortly.

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